Using present semiconductor fabrication technology, problems arise with circuits comprising of selectively grown semiconducting material, such as selectively grown epitaxial (SEG) silicon, in regions encompassed by an insulating material. Because the SEG material is selectively grown on the seed semiconductor material beneath it, such as a silicon substrate, the two materials form a very good crystalline structure match with a defect free interface. This is not true for the interface between the selectively grown semiconductor material and the encompassing insulating material. The selectively grown semiconducting material usually has a non ideal, defective, interface with its neighboring oxide or insulator sidewalls. This semiconductor/insulator sidewall interface lacks strong chemical bonds between the two materials, resulting in a high concentration of semiconductor dangling bonds and electrically active surface states or traps at the interface.
The problem becomes particularly troublesome in the case in which the semiconducting material is comprised of two, oppositely doped, semiconducting materials, thus, forming an active device junction. The device leakage that occurs due to the surface states or dangling bonds between the sidewalls of the selectively grown semiconducting material and the field insulating material can seriously degrade the overall device performance. This interface induced leakage current will result in a substantial increase in reverse junction leakage current, and will also degrade the forward current versus voltage characteristics of the device.
One technique used in an attempt to reduce this sidewall leakage problem is a post SEG anneal in an oxygen ambient. However, oxygen annealing cannot significantly reduce the leakage problem (and in some instances it may increase the leakage problem) because of the possible stresses introduced by the thermal oxidation process.
As a result of the poor semiconductor/insulator sidewall interface and the associated sidewall leakage problem, the device p-n junctions (or Schottky contacts) and depletion layers are usually kept away from the SEG sidewalls, particularly in minority carrier devices, such as bipolar transistors. This method is not acceptable for some applications due to the larger device layout area required because of the addition of the buffer spacer regions between the active device junction region and the selectively grown semiconductor sidewalls.